A phase-locked loop (PLL) is a technology to implement, by using a feedback control principle, that a phase difference between two signals keeps unchanged. For example, for two signals: a first signal and a second signal, a target phase difference between the two signals may be given arbitrarily, that is, a target time interval between a specified time point of the first signal and a preset time point of the second signal is given, and a current phase difference between the two signals is detected, that is, a current time interval between the specified time point of the first signal and the preset time point of the second signal is detected; and when the second signal is used as a reference signal, a phase of the first signal may be controlled according to the target time interval and the current time interval, so as to lock a time interval between the specified time point of the first signal and the preset time point of the second signal, that is, a phase difference between the two signals is locked.
In the phase-locked loop, an apparatus used to detect the current phase difference between the two signals, that is, to detect the current time interval between the specified time point of the first signal and the preset time point of the second signal is a time-to-digital converter (TDC). A time-to-digital converter in the prior art is shown in FIG. 1, mainly including a delay unit 101 into which a first signal is input and a sampling unit 102 into which a second signal is input, where in the first signal and the second signal, the second signal is a reference signal. The delay unit 101 includes multiple delayers with same delay duration that are connected in series, and is configured to delay the first signal, where delay duration of the delay unit 101 is greater than a cycle of the first signal. The sampling unit 102 is configured to: perform sampling on output signals D(1), D(2), . . . , D(n) of the delayers in the delay unit 101 at a preset time point of the second signal, and output sampled signals Q (1), Q(2), . . . , Q(n). A binary sequence Q[1:n] is formed by the sampled signals output by the sampling unit 102 carries information about a time interval between a rising edge time point/falling edge time point of the first signal and the preset time point of the second signal, that is, carries information about a phase difference between the two signals.
It is assumed that delay duration of a delayer is t1 and the cycle of the first signal is T1=8t1, the delay unit 101 needs to include at least eight delayers, for example, may include 10 delayers. The first signal, the second signal, and output signals D(1), D(2), . . . , D(10) of the 10 delayers are shown in FIG. 2, where all the output signals of the 10 delayers are in a same direction as that of the first signal. If the preset time point of the second signal is specifically a rising edge time point of the second signal, the sampling unit 102 performs sampling on the output signals of the 10 delayers in the delay unit 101 at the rising edge time point of the second signal. As shown in FIG. 2, at the rising edge time point of the second signal, the output signals D(1) and D(2) of the delayers are at a high level, D(3), D(4), D(5), and D(6) are at a low level, and D(7), D(8), D(9), and D(10) are at a high level. Therefore, a binary sequence Q[1:10] formed by sampled signals Q(1), Q(2), . . . , Q(10) output by the sampling unit 102 is 0011110000. The binary sequence carries information about time intervals between the rising edge time point of the second signal and the rising edge time point of the first signal, and between the rising edge time point of the second signal and the falling edge time point of the first signal. The first bit in the sequence is “0”. The third bit hops to “1” after a time interval of two delayers from the first bit, which indicates that a time interval between the rising edge time point of the second signal and a falling edge time point of a first signal that is before and nearest to the rising edge time point of the second signal is the time interval of two delayers, that is, 2t1; and the seventh bit re-hops to “0” after a time interval of six delayers from the first bit, which indicates that a time interval between the rising edge time point of the second signal and a rising edge time point of the first signal that is before and nearest to the rising edge time point of the second signal is the time interval of six delayers, that is, 6t1.
Apparently, detection accuracy of an existing time-to-digital converter depends on the delay duration t1 of a delayer in the delay unit 101. If a delayer with relatively small delay duration is used, a large quantity of delayers are required, a cumulative impact of errors on the delayers is relatively large, and it is very difficult to implement the time-to-digital converter; therefore, a delayer with relatively large delay duration needs to be used, which causes relatively low detection accuracy of the existing time-to-digital converter, so that phase locking accuracy of the phase-locked loop is also relatively low.